1. Field of the Invention
The present invention relates to a semiconductor device and a testing method of the same.
2. Description of Related Art
Generally, in manufacturing semiconductor storages a screening test for examining whether memory cells in a semiconductor wafer operate correctly is performed. In this screening test, the IO (input/output) pins of the measuring apparatus are connected in one-to-one correspondence with the IO driver of the semiconductor chip. The measuring apparatus writes in data by way of the IO driver into the memory cell corresponding to the IO driver and reads out the written data. The measuring apparatus, based on the read-out data, determines whether the memory cell is good or not.
Examining whether the memory cells are good or bad, from one cell to another, needs a very long time for a screening test. To reduce the time required for a screening test, a multi-cell test mode for examining whether a plurality of memory cells are good or bad in parallel has been used.
In the multi-cell test mode, data is written into a plurality of IO lines from one DQ terminal of the semiconductor chip. When data is written in this way, the DQ terminal or IO lines are called as being reduced.
In a semiconductor storage, the number of IO lines (the number of lines that are reduced) that are reduced to a single DQ terminal has been determined in accordance with the number of memory cells that can be read out or written in parallel. Specifically, the number of degeneration cannot be set to be equal to or lower than the number of Y switches that can be changed over by a common Y-switch changeover signal. The reason is that if the number of degeneration is set at that number or lower, it becomes impossible to perform individual reading/writing of data into or from each of memory cells into which data is written or from which data is read out, in parallel when a Y-switch is connected by activating a certain Y-switch changeover signal.
The Y-switch herein indicates the switch for changing over connection between the sense amplifier connected to the memory cell and the IO line. Also, usually, IO lines are formed in a pair of complementary IO lines to which two signal lines having a mutually complementary relationship are connected. Accordingly, a Y-switch that switches between one sense amplifier connected to one memory cell and the IO line corresponds to a pair of complementary IO lines.
Now, an example of a semiconductor storage in which a single Y-switch changeover signal is commonly supplied to four sets of Y-switches that connects four sense amplifiers and four pairs of complementary IO lines, or a semiconductor storage which performs data reading/writing in parallel for four memory cells by activating a single Y-switch changeover signal is provided. FIG. 1 is a configurational diagram showing a memory cell array configuration in this semiconductor storage.
In FIG. 1, a single Y-switch changeover switch (e.g., Y-switch changeover switch PYS1) is turned on, complementary signal lines PWRDAT0˜3 and PWRDAB0˜3 to which data is supplied from four IO lines are connected to sense amplifiers PSA0˜3 that correspond to the Y-switches controlled by the Y-switch changeover signal. As a result, a single Y-switch changeover signal causes data supplied from four IO lines to be written into four memory cells in parallel.
FIG. 2 shows a configurational diagram showing a write control circuit for testing whether memory cells in the memory cell array shown in FIG. 1 are good or bad. Here, IO lines PWDA0˜PWDA3 in FIG. 2 correspond to four IO lines for supplying data to complementary signal lines PWRDAT0˜3 and PWRDAB0˜3 in FIG. 1.
In FIG. 2, 16 DQ terminals DQ0˜15 are reduced to four IO lines. In testing whether memory cells are good or bad, if the same data is written into all the memory cells form which data is read out and into from which data is written, in parallel, based on activation of one Y-switch changeover signal, and if data is inverted in all the memory cells, then these memory cells are determined to be good by mistake.
Accordingly, the measuring apparatus needs to input data separately to DQ terminals PDQ0˜3 so as to write data individually to the four memory cells from which data can be read out and into which data is written, in parallel, based on activation of one Y-switch changeover signal.
In order to input data separately to the memory cells which are readable and writable in parallel based on activation of one Y-switch changeover signal, four IO pins of the measuring apparatus are allotted to this semiconductor storage so that these four IO pins are connected to DQ terminals PDQ0˜3. The measuring apparatus reads data from and writes into the memory cells via respective DQ terminals PDQ0˜3 so as to test whether the memory cells are good or bad.
FIG. 3 is a timing chart for illustrating the operation of the write control circuit shown in FIG. 2. Herein, it is assumed that DQ terminals PDQ0˜3 in FIG. 2 are connected to the measuring apparatus.
When TMD (test mode) signal is activated, the data input to DQ terminals PDQ0˜3 are respectively output to IO lines PWDA0˜3 corresponding to DQ terminals PDQ0˜3 and to the IO lines which are degenerated to DQ lines and correspond thereto. For example, the data input to DQ terminal PDQ0 is output to IO line PWDA0 corresponding to DQ terminal PDQ0, IO line PWDA4 corresponding to DQ terminal PDQ4, IO line PWDA8 corresponding to DQ terminal PDQ8 and IO line PWDA12 corresponding to DQ terminal PDQ12.
The data input to each IO line is latched based on PCLK signal as a clock pulse that is generated in synchronization with the Rise edge (leading edge) of CLK (clock) signal. The data thus latched is input to complementary signal lines PWRDAT0˜3 and PWRDAB0˜3 when WRT signal that is generated when a write command (writing instruction) is presented as an external command. Then, the input data is written into the memory cells.
The circuit for reading out the written data in memory cells outputs the EXNOR of the data in the memory cells (e.g., the memory cells corresponding to DQ terminals DQ0, DQ4, DQ8 and DQ12) corresponding to the IO lines connected to DQ terminals which have each been reduced. As a result, when all these data are same, the H-level signal is output, otherwise the L-level signal is output. The measuring apparatus determines that the memory cells are good when the H-level signal is output and that the memory cells are bad when the L-level signal is output.
In recent years, in order to further reduce memory cells in size, semiconductor storages in which data is read out from and written into eight memory cells in parallel based on one switch changeover signal, have been in circulation. FIG. 4 is a configurational diagram showing a memory cell array in such a semiconductor storage.
In the above multi-cell measuring test mode, DQ terminals are reduced into the number of the memory cells which are read out and written in based on activation of one Y-switch changeover signal. Accordingly, in the semiconductor storage shown in FIG. 4, DQ terminals are degenerated into eight DQ terminals.
Accordingly, it is necessary to change the number of IO pins allotted to the semiconductor storage depending on the number of memory cells which are read out and written in, in parallel.
Literature 1 (Japanese Patent Application Laid-open 2003-132681) discloses a semiconductor storage in which the same number of IO pins are allotted even though the number of memory cells that are read out and written in parallel based on activation of a Y-switch changeover signal differs.
In this semiconductor storage, when data is read out from or written into four memory cells in parallel based on activation of one Y-switch changeover signal, each data item input through four DQ terminals are expanded four times. When data is read out from or written into eight memory cells in parallel based on activation of one Y-switch changeover signal, each data item input through four DQ terminals are expanded eight times. Accordingly, eight DQ terminals can be reduced to four DQ terminals.
As a result, it is possible to allot the same number of IO pins even though the number of memory cells which are read out from and written in in parallel based on activation of a Y-switch changeover signal differs.
Recently, a further reduction in price of semiconductor storages has been desired. In answer to this demand, it is necessary to reduce the cost of semiconductor storages. It is expected that if the time taken for screening tests can be further shortened, the cost of semiconductor storages can be reduced.
In order to further shorten the time for screening tests, we discovered that it is necessary to further increase the number of memory cells (which will be referred to hereinbelow as multi-measurement number) whose quality can be tested at the same time.
Since if the number of IO pins of the measuring apparatus is increased, the number of semiconductor storages that can be connected to the measuring apparatus at the same time increases, it is possible to increase the multi-measurement number. However, we discovered the problem that, if the number of IO pins of the measuring apparatus increases, the cost for the measuring apparatus increases, hence it is impossible to reduce the cost of the memory.
Further, the method of increasing the number of DQ terminals to be degenerated by expanding each data item input to four DQ terminals eight times, as in the semiconductor storage described in literature 1, can also be considered. However, we discovered that this method entails the problem that it is impossible to write data individually to the memory cells into which data is written or form which data is read out in parallel when one Y-switch changeover signal is activated.